Flash memories are high density non-volatile memories and may be divided into data flash and code flash memories.
Data flash memories are typically used for storing large data volumes in applications such as digital cameras, MP3 players and other electronic products. These applications require a large numbers of cells in each sector. The requirements regarding the reliability of data flash memories are less strict than for code flash memories. In order to minimize the area required for each memory cell, NAND architectures are used. However, NAND architectures lead to slower access times.
Code flash memories are typically used for storing program code in applications such as personal computers, mobile telephones, personal digital assistants and other electronic devices. This type of memory needs to meet higher reliability demands than data flash memories. NOR architectures are used to reduce access times. As smaller portions of memories need to be accessible for read, write or erase operations, sectors in code flash memories are smaller than in data flash memories.
The storage capacity of flash memories can be increased by increasing the number of bits stored per cell. Nitride programmable read only memory (NROM) cells can store two bits per cell and are based on charge trapping in a nitride layer of an ONO (oxide-nitride-oxide) gate dielectric. Charge is localized in two regions of the nitride layer of each cell and the charge stored in each region can be manipulated independently. For each region, the amount of electrical charge stored determines the threshold voltage values Vth of the cell. A high threshold value Vth corresponds to a high ‘1’ state and a low threshold value Vth ‘0’ to a low state. By applying a gate voltage that is between the high and low threshold voltage and sensing the current flowing through the transistor, the state stored in each region of the NROM cell can be determined. Apart from being able to store two bits per cell, NROM cell based memories further have the advantage of requiring minimal electrical power and a low production complexity.
In contrast to other flash memory technologies which depending on the type of flash memory use either a NOR or NAND architecture, NROM based memories can use the so-called “virtual ground array” architecture for both data flash and code flash memories. FIG. 1 shows such a virtual ground array 26. Individual memory cells 23 are arranged along rows and columns to form a matrix. The gates of memory cells 23 arranged along rows are connected by word lines 3. The drain and source contacts of memory cells 23 arranged along columns are connected to bit lines 4, with each bit line 4 being shared between two neighboring cells (23) along rows. Each memory cell 23 in the array 26 can be selected by the respective word line 3 and bit lines 4 corresponding to the row and the column in which the memory cell is located.
Memory cells are usually grouped together in sectors so that operations, such as erasing, may easily and simultaneously be preformed on a large number of memory cells. In general a word line will pass through more than one sector, connecting the gate electrodes of memory cells belonging to different sectors. Because of the shared word line common to memory cells of plural sectors, not only the memory cells in the sector that is to be erased are biased with a high negative or positive voltage at the gate necessary for this operation. In addition, also memory cells of other sectors not to be erased but connected to the same word line are biased. The states stored in memory cells of these sectors will usually not be changed because no voltage is applied to their bit lines. However, the voltage applied to the gates of the non-selected memory cells are high enough to affect the electric charge stored in the ONO layer of the memory cells over a large number of such program or erase cycles. As a result, the threshold voltages Vth in those cells change so that it is no longer possible to distinguish between the high and low state. This is known as “gate disturb” and can lead to wrong values being read out from the memory cells.
In most flash memory products gate disturb is not suppressed even though it leads to reduced reliability of the memory. Efforts to reduce the effects of gate disturb include optimizing the thickness of, for example, the ONO layer. In another approach word lines are divided into separate word lines for each sector. The gates of the cells to be erased are connected to a word line by using a sector specific select transistor. However, this approach leads to more complicated memory constructions.